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for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 1 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll features functional diagram ? fractional or i nteger modes ? 8 ghz, 16-bit r f n - c ounter ? 24-bit step size r esolution, 3 hz typ ? ultra low phase n oise 6 ghz, 50 mhz r ef. -103 / -110 dbc/hz @ 20 khz (frac / i nteger) ? r eference path i nput: 200 mhz ? 14-bit r eference path divider ? low fractional spurious ? r eference spurs: -90 dbc typ ? a uto and t riggered sweeper functions ? c ycle slip prevention ( c sp) for fast settling ? a uxiliary c lock source ? 40 lead 6x6 mm sm t package: 36 mm2 t ypical a pplications ? base stations for mobile r adio (gsm, p c s, d c s, c dm a , w c dm a ) ? wireless l an s, wimax ? c ommunications t est equipment ? cat v equipment ? fm c w sensors ? a utomotive r adar ? phased- a rray systems
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 2 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 1. electrical specifcations parameter c onditions / n otes min t yp max units prescaler characteristics max r f i nput frequency (3.3v) 8 9 ghz max r f i nput frequency (2.7 - 3.3v) 7 8 ghz min r f i nput frequency 0.1 mhz r f i nput power -10 -6 10 dbm 16-bit n -divider r ange ( i nteger) 32 65,535 16-bit n -divider r ange (fractional) fraction n ominal divide ratio varies (-3 / +4) dynamically max 35 65,531 ref input characteristics max r ef i nput frequency (pin x r efp) 250 200 mhz max r ef i nput frequency (pin xs in ) 250 220 mhz min r ef i nput frequency 50 ? source. xs in minimum 20mhz due to phase noise degra - dation 100 khz r ef i nput voltage r ange (pin x r efp) ac c oupled 750 1000 3300 mvpp r ef i nput power r ange (pin xs in ) -6 0 12 dbm r ef i nput c apacitance 5 pf 14-bit r -divider r ange 1 16,383 general description t he hm c 701lp6 c e is a sige bi c m o s fractional- n pll. t he pll includes a 8ghz 16-bit r f n -divider, a 24-bit delta- sigma modulator, a very low noise digital phase frequency detector (pfd), and a precision controlled charge pump. t he fractional- n pll features an advanced delta-sigma modulator design that allows ultra-fne frequency step sizes. t he fractional- n pll features the ability to alter both the phase-frequency detector (pfd) gain and the cycle slipping characteristics of the pfd. t his feature can reduce the time to arrive at the new frequency by 50% vs. conventional pfds. ultra low in-close phase noise also allows wider loop bandwidths for faster frequency hopping. t he fractional- n pll contains a built-in linear sweeper function, which allows it to perform frequency chirps with a wide variety of sweep times, polarities and dwells, all with an external or automatic sweep trigger. i n addition the fractional- n pll has a number of auxiliary clock generation modes that can be accessed via the gp o . electrical specifcations, t a = +25 c v cc hf = v cc p r s = r vdd = +3.3v vpp c p = v ccoa = vddpd r = vppd r v = vddpd = vddpdv = +5v dvdd = dvdd io = dvddq = +3.3v gn dd r v = gnd c p = gn dpd = gn dpdv = gn dpd r = 0v
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 3 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 1. electrical specifcations parameter c onditions / n otes min t yp max units phase detector fractional mode phase detector frequency 0.1 70 mhz i nteger mode phase detector frequency 0.1 100 mhz charge pump max o utput c urrent 4 m a min o utput c urrent 125 a c harge pump gain step size (5-bits) 125 a c harge pump t rim step size (3-bits) 14 a c harge pump o ffset step size (4-bits) 29 a pfd / c harge pump n oise ( i nteger) 6 ghz, 50 mhz r ef, i nput referred 1 khz -141 dbc/hz 10 khz -149 dbc/hz 100 khz -155 dbc/hz c ompliance voltage less than 3 db degradation typ. at these limits -406 a o ffset 0.4 vpp c p-0.8 v -406 a o ffset 0.8 vpp c p-0.4 v logic inputs v i h i nput high voltage vdd io -0.4 v v i l i nput low voltage 0.4 v logic outputs v i h o utput high voltage vdd io -0.1 v v i l o utput low voltage 0.1 v power supply voltages v cc - a nalog 3v supplies v cc p r s, r vdd, v cc hf 3 3.3 3.45 v dvdd - digital i nternal supply dvdd, dvddq 3 3.3 3.45 v dvdd io - digital i /o supply dvdd io 1.8 3.3 5.5 v a nalog 5v supplies v ccoa , vpp c p, vppd r v, vddpd, vddpdv, vddpd r 4.5 5.0 5.5 v power supply current (6 ghz fractional mode, 50 mhz pfd) a nalog +5v v ccoa , vpp c p, vppd r v, vddpd, vddpdv, vddpd r 37 m a a nalog +3.3v v cc p r s, r vdd, v cc hf 71 m a digital +3.3v dvdd, dvdd io , dvddq 19 m a power down - c rystal o ff r eg 01h = 0 c rystal not clocked 6 a power down - c rystal o n, 100 mhz r eg 01h = 0 c rystal clocked 100 mhz 20 200 a (continued)
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 4 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 1. electrical specifcations parameter c onditions / n otes min t yp max units temperature sensor (3-bit) min t emperature r eadout: 000 -32 c max t emperature r eadout: 111 +82 c t emp c hange / lsb 17.5 c /lsb worst c ase a bsolute t emp error 10 c c urrent c onsumption (when enabled) 2 m a power on reset t ypical r eset voltage on dvdd 700 mv min dvdd voltage for n o r eset 1.5 v closed loop phase noise 6 ghz v co , i nteger, 50 mhz pfd 1 khz offset -98 dbc/hz 6 ghz v co , i nteger, 50 mhz pfd 10 khz offset -108 dbc/hz 6 ghz v co , i nteger, 50 mhz pfd 100 khz offset -110 dbc/hz 6 ghz v co , fractional, 50 mhz pfd 1 khz offset -93 dbc/hz 6 ghz v co , fractional, 50 mhz pfd 10 khz offset -103 dbc/hz 6 ghz v co , fractional, 50 mhz pfd 100 khz offset -105 dbc/hz closed loop phase noise n ormalized to 1 hz i nteger mode measured with 50 mhz pfd -227 dbc/hz fractional mode measured with 50 mhz pfd -221 dbc/hz (continued) t able 2. a bsolute maximum r atings parameter rating r vdd, v cc hf, dvdd, dvddq, v cc p r s -0.3 to +3.6v v ccoa , vpp c p, vppd r v, vddpd, vddpdv, vddpd r , dvdd io -0.3 to +6v o perating t emperature -40 to +85 c storage t emperature -65 to +120 c maximum junction t emperature +125 c t hermal r esistance ( r th) 20 c /w r efow soldering peak t emperature 260 c t ime at peak t emperature 40 sec esd sensitivity (hbm) c lass 1b stresses above those listed under a bsolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 5 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 3. pin description pin n o. pin n ame p i n t ype description 1 v cc p r s supply r f prescaler power supply. n ominally +3.3v 2 v ccoa supply c hargepump o p a mp power supply. n ominally +5v 3 vpp c p supply power supply for c harge pump. n ominally +5v 4 c p a nalog o /p c harge pump output 5 g n d c p g n d power supply g n d for c harge pump 6 g n dd r v g n d c harge pump g n d 7 vppd r v supply power supply for c harge pump, n ominally +5v 8 vddpd supply power supply for phase detectors, n ominally +5v 9 g n dpd g n d power supply g n d for phase detector 10, 20, 21, 26 n / c n / c n o c onnection 11 vddpdv supply power supply for phase detector v co path, n ominally +5v 12 g n dpdv g n d power supply g n d for phase detector v co path 13 vddpd r supply power supply for phase detector r ef path, n ominally +5v 14 g n dpd r g n d power supply g n d for phase detector r ef path 15 x r efp a nalog i /p square wave c rystal r ef i nput 16 r vdd supply power supply for r ef path, n ominally +3.3v 17 xs in a nalog i /p sinusoidal c rystal reference input 18 r ef ca p a nalog i / o r eference path bypass 19 r s t b c m o s i /p r eset i nput (active low) 22 dvdd supply digital power supply, n ominally +3.3v 23 gp o 1 d o general purpose o utput 1 with t ristate 24 gp o 2 d o general purpose o utput 2 with t ristate 25 gp o 3 d io general purpose i nput/ o utput with t ristate may be confgured for external r amp trigger i nput. see register r eg 14h[5] 27 se n c m o s i /p main serial port enable input 28 sd i c m o s i /p main serial port data input 29 s c k c m o s i /p main serial port clock input 30 vsle d o leave pin disconnected. 31 vsd o d o leave pin disconnected. 32 vs c k d o leave pin disconnected. 33 ld_sd o c m o s o /p lock detect or main serial port data o utput 34 dvdd io supply power supply for digital i / o , matches external digital supply in 1.8v to 5.5v range 35 dvdd supply i nternal digital power supply. n ominally 3.3v 36 dvddq supply power supply i solation pin. n ominally 3.3v, bypassed to g n d, zero current. 37 v coi p r f i /p c omplementary i nput to the r f prescaler. i f single ended input, this point must be decoupled to the ground plane with a ceramic bypass capacitor, typically 100 pf 38 v coin r f i /p i nput to the r f prescaler. t his signal input is ac-coupled to the external v co 39 v cc hf supply r f section power supply. n ominally 3.3v 40 b ia s a nalog i /p decoupling pin for r f section, nominally external 1nf bypassed to v cc hf
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 6 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t ypical phase n oise - i nteger mode t ypical phase n oise - fractional mode r f divider sensitivity frequency sweep c ycle slip prevention: frequency hop from 5200 mhz to 3950 mhz -170 -160 -150 -140 -130 -120 -110 -100 -90 1000 10 4 10 5 10 6 10 7 10 8 all plots 50 mhz pfd frequency (hz) 2 ghz fractional 6 ghz fractional phase noise (dbc/hz) 3900 4100 4300 4500 4700 4900 5100 5300 -10 0 10 20 30 40 50 60 70 time (s) csp on csp off frequency (mhz) 5850 5900 5950 6000 6050 6100 6150 -2 -1 0 1 2 3 time (ms) frequency (mhz) -170 -160 -150 -140 -130 -120 -110 -100 -90 1000 10 4 10 5 10 6 10 7 10 8 all plots 50 mhz pfd frequency (hz) 2 ghz integer 6 ghz integer 1 ghz integer phase noise (dbc/hz) -40 -30 -20 -10 0 10 20 0 2000 4000 6000 8000 10000 frequency (mhz) +85c +25c -40c frac integ frequency (mhz) input power (dbm)
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 7 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll 1. r eference path i nput buffers 2. r eference path divider 3. v co path i nput buffer 4. v co path multi-modulus prescaler/divider 5. ? fractional modulator 6. phase frequency detector 7. c harge pump 8. main serial port 9. v co serial port for stepped v co support 10. t emperature sensor 11. power o n r eset c ircuit 12. c w sweeper subsystem 13. a uxiliary c lock generator 14. general purpose o utput (gp o ) bus 15. multiple v co c ontroller t heory of o peration t he hm c 701lp6 c e synthesizer consists of the following functional blocks each of these blocks is described briefy in the following section. r eference path t he full r eference path block diagram is shown in figure 1 t he ultra low noise phase detector requires the best possible reference signal. since a given application may desire to use a square wave or a 50 o hm sinusoidal crystal source, hm c 701lp6 c e offers two input ports, each one optimized for the lowest possible noise for the source type being used. for absolute best low noise performance, the sine wave path should be used. t he user should use only one r ef path input, that is the input that matches their reference source type. n ote the input is defaulted to the square wave input on power up. should the sine reference path be used, it is necessary to enable the sine input, shut down the square wave input and set the mux ( rfp_buf_sin_en=1, rfp_buf_sq_en=0, rfp_buf_sin_ sel=1 , t able 12 ). t he unused port should be left open. t he reference path supports input frequencies of up to 250 mhz typical, however the maximum frequency at the phase detector (pfd) depends upon the mode of operation, worst case at +85 c , 70 mhz in fractional mode and 100 mhz in integer mode. hence reference inputs of greater than the pfd maximum frequency must use the appropriate r divider setting. figure 1 . reference sine input stages t he unused reference port is normally not connected.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 8 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll sine r eference i nput t he crystal reference sine input stage is shown in figure 2. t his is the lowest noise reference path. t his is a common emitter single ended bipolar buffer. t he xs in input pin is d c coupled and has about 950 mv bias on it. expected input is a 0 dbm sinusoid from a 50 o hm source. n ormally the input should be ac coupled externally. t he sine buffer input impedance is dominated by a 25 o hm shunt resistor in series with a 50 pf on chip cap. should a lower input impedance be needed, an external 50 o hm shunt resistor can be used, d c isolated by an external bypass cap. t he sine input reference path phase noise foor is approximately equivalent to -159 dbc/hz. for best performance care should be taken to provide a crystal reference source with equivalent or better phase noise foor. figure 2 . ref sine input square wave r eference i nput t he square wave r ef i nput stage is shown in figure 3. t he stage is designed to accept square wave inputs from c ml to c m o s levels. slightly degraded phase noise performance may be obtained with quasi sine 1 vpp inputs. i t may be necessary to attenuate very large c m o s levels if absolute best in close phase noise performance is required. i nput reference should have a noise foor better than -160 dbc/hz to avoid degradation of the input reference path. figure 3 . square wave ref input stage
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 9 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll r eference path r divider t he referenced path features a 14-bit divider ( rfp_div_ratio, reg03h<13:0> t able 14 ) and can divide input signals at up to 250 mhz by numbers from 1 to 16,383. t he selected input reference source may be divided or bypassed ( rfp_div_select ), and applied to the phase detector reference input. r eference path t est features a fractional synthesizer is a complex combination of a low phase noise analog oscillator running in close proximity with a nearly randomly modulated delta-sigma digital modulator. c lean spur free operation of the synthesizer requires proper board layout of power and grounds. spurious sources are often difficult to identify and may be related to harmonics of the digital modulation which land near the operating frequency of the v co , or they may arise from repeating patterns in the digital modulation itself . t he loop flter and the fractional modulator are designed to suppress these fractional spurs, but it is sometimes the case that the isolation of the spurious products comes from layout issues. t he problem is how to identify the sources of spurious products if they occur? t he reference path of the hm c 701lp6 c e features some interesting test options for clocking the digital portion of the synthesizer which may provide for a better understanding of the source of reference spurs should they occur. see figure 4, t able 12 and t able 29 for more register details. i t is possible for example to set the synthesizer to integer mode of operation, where the digital harmonics normally fall directly on the v co frequency. we might chose for example to use the sine source ( rfp_buf_sine_sel=1, div_ todig_en=0 ) to drive the reference divider. i n such a case the delta sigma modulator is not normally used, however if we wish to test the effects of the digital power supply isolation, we could input a 2 nd reference source on the square wave input, enable its buffer ( rfp_buf_sq_en=1 ), and enable the 2 nd crystal to clock the unused delta sigma modulator ( sqr_todig_en=1 and dsm_xref_sin_select=0 ). t his would allow the square wave clock to be set independently of the locked integer mode v co , and hence measure the coupling of the digital to the sidebands of the v co at various frequencies. such a test can help in identifying and debugging grounding and layout issues in the application circuit related to the digital portion of the p c b should they occur. i n general it is recommended to follow the suggested layout closely to avoid any such problems. figure 4 . reference path block diagram v co path t he r f path from the v co to the phase detector, is referred to as the v co path. t he v co path consists of an input isolation buffer and a multi-modulus prescaler, or simply the n divider. t he n divider is controlled by the fractional modulator. t his path operates with inputs directly from the external v co .
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 10 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll rf i nput stage t he synthesizer r f input stage routes the external v co to the phase detector via a 16-bit fractional divider. t he r f input path is rated to operate nominally from 100 khz to 8 ghz in fractional and 9 ghz in integer modes. t he r f input stage also provides isolation between the v co and the prescaler. t he r f input stage is a differential common emitter stage, d c coupled for maximum fexibility. t he input is protected by esd diodes as shown in figure 5. n ormally the r f input is ac coupled to a single ended external source. t he r f in p buffer is well matched from a single ended 50 o hm source above about 3.5 ghz, with the complimentary input grounded. i f a better match is required at low frequency a simple shunt 50 o hm resistor can be used external to the package. i f a differential external source is used then the two input pins may be used for best performance. figure 5 . rf input stage r f path n divider t he main r f path divider is capable of average divide ratios between 65,531 and 36 in fractional mode, and 65,535 to 32 in integer mode. t he reason for the difference between integer and fractional modes is that the fractional divider actually divides by up to 4 from the average divide number. a ctual division ratios when used with a given v co will depend upon the reference frequency used and the desired output band. general purpose o utput (gp o ) i nterface t he hm c 701lp6 c e features a 3-wire general purpose o utput (gp o ) interface. gp o registers are described in reg1bh t able 37 . t he gp o is a fexible interface that supports a number of different functions and real time waveform access including: a. general data o utput from sp i register gpo_sel_0_ data (gpo_sel=0) b. prescaler & reference path outputs (gpo_sel=1) c. lock detect windows (gpo_sel=2) d. a nti-cycle slip waveforms (gpo_sel=3) e. i nternal synchronized frac strobe with clocks (gposel=4) f. ? modulator phase a ccumulator (gposel=6) g. a uxiliary oscillators (gposel=7) h. ? modulator o utputs (gposel=10) general data to gp o (gpo_sel=0) setting register gpo_sel=0 in t able 37 assigns the 3-bit data from register gpo_sel_0_data reg1b<6:4> to the gp o bus.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 11 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll prescaler and r eference path o utputs (gpo_sel = 1) setting register gpo_sel=1 ( reg1b<3:0> t able 37 ) results in the input crystal being buffered out to gp o 3 as shown in figure 6. t his is useful for example to generate a copy of the input crystal signal to drive other circuits in the application, while at the same time isolating the noisy circuits from the sensitive crystal output. o ften only the synthesizer requires very low phase noise from the crystal, hence it is desirable to isolate other circuits from the crystal itself and allow the synthesizer sole use of the low phase noise crystal. gpo_sel=1 also routes the 250 mhz 14-bit reference path divider to gp02 and the 16-bit 7 ghz v co path prescaler output to gp01. t his option allows the synthesizer to function as a stand alone fractional or integer prescaler and provides visibility into the prescaler and reference path timing for sensitive applications. figure 6 . gpo_01 outputs l ock detect windows (gpo_sel=2) setting register gpo_sel = 2 ( reg1bh<3:0> t able 37 ) results in the lock detect window (figure 11) and the phase frequency detector up and d n output control signals (figure 14) to be routed to pins gp o 1, gp o 3 and gp o 2 respectively. t his option gives insight into the lock detection process and could allow the synthesizer to be used with an external charge pump. figure 7 . gpo_02 outputs
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 12 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll a nti-cycle slip waveforms (gpo_sel = 3) setting register gpo_sel=3 ( reg1bh<3:0> t able 37 ) gives visibility into the anti-cycle slipping function of the pfd as described in section cycle slip prevention ( c sp). t hree waveforms, reference path freq > v co path freq, vco path freq > ref path freq, and a pfd strobe which holds the pfd at maximum gain, are routed to gp o 3, gp o 2, and gp o 1 respectively. t hese lines will be active during frequency pull-in and will indicate instantaneously which signal, reference or vco path is greater in frequency. t he pfd strobe gives insight into when the pfd is near maximum gain at 2. t he pfd strobe will be active until the v co pulls into lock. i nternal synchronized frac strobe with clocks (gpo_sel= 4) setting register gpo_sel=4 in ( reg1bh<3:0> t able 37 ) gives visibility into the internally synchronized strobe that is generated when commanding a frequency change by writing to the frac register. t he internal strobe initiates the update to the fractional modulator. t he internal frac strobe, the ref path divider output and the sine reference input are buffered out to gp o 1,gp o 2 and gp o 3 respectively as shown in figure 8. i n this mode, gp o 1 may be used to trigger an external instrument when doing frequency hopping tests for example. figure 8 . gpo_04 outputs modulator phase a ccumulator (gpo_sel=6) setting register gpo_sel=6 ( reg1bh<3:0> t able 37 ) assigns the three msbs of the delta sigma modulator frst accumulator to gp o <3:1>, where gp o 3 is the msb. t his feature provides insight into the phase of the v co . a uxiliary o scillators (gpo_sel=7) setting register gpo_sel=7 ( reg1bh<3:0> t able 37 ) assigns an auxiliary clock, an internal ring oscillator, and the internal sigma delta clock to gp o 3, 2, 1 respectively. t he control of the auxiliary clock is determined by r eg18h t able 34 and reg19h t able 35 . i n general terms, this highly fexible clock source allows the selection of one of the various v co or crystal related clocks inside the synthesizer or the selection of a fexible unstabilized auxiliary ring oscillator clock. a ny of the sources may be routed out via gpo_sel=7. a dditional reg18h t able 34 clock controls allow the aux clock to be delayed by a variable amount (auxclk_modesel reg18h<3:2>) , or to be divided down by even values from 2 to 14 (auxclk_divsel reg18h<6:4>) .
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 13 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll modulator o utputs (gpo_sel=10) setting register gpo_sel=10 ( reg1b<3:0> t able 37 ) assigns the three lsbs of the delta sigma modulator output to gp o <3:1> , where gp o 1 is the lsb. t his feature allows the possibility of using the hm c 701lp6 c e as a general purpose digital delta sigma modulator for many possible applications. external v co t he hm c 701lp6 c e is targeted for ultra low phase noise applications with an external v co . t he synthesizer has been designed to work with v co s that can be tuned nominally over 0.5 to 4.5 volts on the varactor tuning port with a +5v charge pump supply voltage. slightly wider ranges are possible with a +5.5v charge pump supply or with slightly degraded performance. a n external opamp active flter is required to support v co s with tuning voltages above 5v. external v co with a ctive i nverting o p a mp l oop filter a n external opamp active flter is required to support external v co s with tuning voltages above 5v. i f an inverting opamp is used with a positive slope v co , phase_sel r eg05h <0> = 1 t able 16 must be set to invert the pfd phase polarity and obtain correct closed loop operation. t emperature sensor t he hm c 701lp6 c e features a built in temperature sensor which may be used as a general purpose temperature sensor. t he temperature sensor is enabled via tsens_spi_enable ( reg1eh=1 t able 40 ) and when enabled draws 2 m a . t he temperature sensor features a built in 3-bit quantizer that allows the temperature to be read in register tsens_ temperature ( reg21h t able 43 ). t he temperature sensor data converter is not clocked. updates to the temperature sensor register are made by strobbing register tsens_spi_strobe ( r eg00h<3> t able 11 ). t he 3-bit quantizer operates over a -40 c to +100 c range as follows: t n = foor {( t emperature +40) / 17.5 where t n is the decimal value of register tsens_temperature} (eq 7) 0 1 2 3 4 5 6 7 -40 -20 0 20 40 60 80 100 temperature (c) temperature sensor quantizer output figure 9 . typical temperature sensor quantizer output t emperature sensor slope is 17.5 mv/lsb. a bsolute tolerances on the temperature sensor thresholds may vary by up to 10 c worst case. n ominal temperature is given by: (eq 8)
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 14 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll c harge pump & phase frequency detector (pfd) t he phase frequency detector or pfd has two inputs, one from the reference path divider and one from the v co path divider. t he pfd compares the phase of the v co path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. t he output current varies linearly over a full 2 radians input phase difference. pfd functions phase_sel ( reg05h<0> t able 16 ) inverts the phase detector, polarity for use with an inverting opamp or negative slope v co . upout_en in reg05h<1> t able 16 allows masking of the pfd up output, which effectively prevents the charge pump from pumping up . dnout_en in reg05h<2> t able 16 allows masking of the pfd down output, which effectively prevents the charge pump from pumping down. c harge pump t ri-state de-asserting both upout_en and dnout_en effectively tri-states the charge pump while leaving all other functions operating internally. pfd jitter & l ock detect background i n normal phase locked operation the divided v co signal arrives at the phase detector in phase with the divided crystal signal, known as the reference signal. despite the fact that the device is in lock, the phase of the v co signal and the reference signal vary in time due to the phase noise of the crystal and v co oscillators, the loop bandwidth used and the presence of fractional modulation or not. t he total integrated noise on the v co path normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. i f we wish to detect if the v co is in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. first, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. t he standard deviation of the arrival time of the v co signal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked v co has a constant phase noise, 2 (? 0 ), at offsets less than the loop 3 db bandwidth and a 20 db per decade roll off at greater offsets. t he simple locked v co phase noise approximation is shown on the left of figure 10. figure 10 . synthesizer phase noise & jitter
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 15 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll with this simplifcation the single sideband integrated v co phase noise, 2 , in rads 2 at the phase detector is given by (eq 9) where 2 ssb (? 0 ) is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, b is the 3 db corner frequency of the closed loop pll and n is the division ratio of the prescaler t he rms phase jitter of the v co in rads, , results from the power sum of the two sidebands: = 2 2 ssb (eq 10) since the simple integral of (eq 9) is just a product of constants, we can easily do the integral in the log domain. for example if the v co phase noise inside the loop is -100 dbc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio n =100, then the integrated single sideband phase noise at the phase detector in db is given by 2 db = 10log ( 2 (? 0 )b ? n 2 ) = -100 + 50 + 5 - 40 = -85 dbrads, or equivalently = 10 -82/20 = 56 urads rms or 3.2 milli-degrees rms. while the phase noise reduces by a factor of 20log n after division to the reference, the jitter is a constant. t he rms jitter from the phase noise is then given by t jnp = t ref / 2 i n this example if the reference was 50 mhz, t ref = 20 nsec, and hence t jpn = 178 femto-sec. a normal 3 sigma peak-to-peak variation in the arrival time therefore would be i f the synthesizer was in fractional mode, the fractional modulation of the v co divider will dominate the jitter. t he exact standard deviation of the divided v co signal will vary based upon the modulator chosen, however a typical modulator will vary by about 3 v co periods, 4 v co periods, worst case. i f, for example, a nominal v co at 5 ghz is divided by 100 to equal the reference at 50 mhz, then the worst case division ratios will vary by 1004. hence the peak variation in the arrival times caused by ? modulation of the fractional synthesizer at the reference will be (eq 11) i n this example, t j?pk = 200 ps(104-96)/2 = 800 psec. i f we note that the distribution of the delta sigma modulation is approximately gaussian, we could approximate t j?pk as a 3 sigma jitter, and hence we could estimate the rms jitter of the ? modulator as about 1/3 of t j?pk or about 266 psec in this example. hence the total rms jitter t j , expected from the delta sigma modulation plus the phase noise of the v co would be given by the rms sum , where (eq 12) i n this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation. i n summary, we have to expect about 0.8 nsec of normal variation in the phase detector arrival times when in fractional mode. i n addition, lower v co frequencies with high reference frequencies will have much larger variations., for example, a 1 ghz v co operating at near the minimum nominal divider ratio of 36, would, according to ( eq 11 ), exhibit about 4 nsec of peak variation at the phase detector, under normal operation. t he lock detect circuit must not confuse this modulation as being out of lock.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 16 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll pfd l ock detect lkd_en ( reg01h<11> t able 12 ) enables the lock detect functions of the hm c 701lp6 c e. t he lock detect circuit in the hm c 701lp6 c e places a one shot window around the reference. t he one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer. c learing lkd_ringosc_mono_select ( reg1ah<14> t able 36 ) will result in a nominal 10nsec analog window of fxed length, as shown in figure 11. setting lkd_ringosc_mono_select will result in a variable length digital widow. t he digital one shot window is controlled by lkd_ringosc_cfg (reg1ah<16:15>) . t he resulting lock detect window period is then generated by the number of ring oscillator periods defned in lkd_monost_duration reg1ah<18:17> ( t able 36 ). t he lock detect ring oscillator may be observed on the gp o 2 port by setting ringosc_testmode ( reg1ah<19> t able 36 ) and confguring the gpo_sel<3:0> = 0111 in ( reg1bh t able 37 ). lock detect does not function when this test mode is enabled. lkd_wincnt_max ( reg1ah<9:0> t able 36 ) defnes the number of consecutive counts of the v co that must land inside the lock detect window to declare lock. i f for example we set lkd_wincnt_max = 1000 , then the v co arrival would have to occur inside the selected lock widow 1000 times in a row to be declared locked. when locked the lock detect fag ro_lock_detect ( reg1fh<0> t able 41 ) will be set. a single occurrence outside of the window will result in clearing the lock detect fag, ro_lock_detect . t he lock detect fag ro_lock_detect ( reg1fh<0> t able 41 ) is a read only register, readable from the serial port. t he lock detect fag is also output to the ld_sdo pin according to lkd_to_sdo_always (reg1ah<13>) and lkd_to_sdo_ automux_en (reg1ah<12>) , both in t able 36 . setting lkd_to_sdo_always will always display the lock detect fag on ld_dso . c learing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display the lock detect fag on ld_sdo except when a serial port read is requested, in which case the pin reverts temporarily to the serial data o ut pin, and returns to the lock detect function after the read is completed. figure 11 . normal lock detect window l ock detect with phase o ffset when operating in fractional mode the linearity of the charge pump and phase detector are more critical than in integer mode. t he phase detector linearity is worse when operated with zero phase offset. hence in fractional mode it is necessary to offset the phase of the reference and the v co at the phase detector. i n such a case, for example with an offset delay, as shown in figure 12, the mean phase of the v co will always occur after the reference. t he lock detect circuit window can be made more selective with a fxed offset delay by setting win_asym_enable and win_asym_up_select ( reg1ah<11> t able 36 ). similarly the offset can be in advance of the reference by clearing win_asym_up_select while leaving win_asym_enable reg1ah<10> set both in t able 36 .
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 17 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll figure 12 . delayed lock detect window for most applications the analog one shot window is sufficient. t o determine the required lock detect one shot window size: r equired ld o ne shot window = ( c p phase o ffset (ns) + 4x t vco) x 1.3 c ycle slip prevention ( c sp) when changing frequencies the v co is not yet locked to the reference and the phase difference at the pfd varies rapidly over a range much greater than 2 radians. since the gain of the pfd varies linearly with phase up to 2, the gain of conventional pfds will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. t his phenomena is known as cycle slipping. c ycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in figure 13. c ycle slipping increases the time to lock to a value far greater than that predicted by normal small signal laplace analysis. t he hm c 701lp6 c e pfd features c ycle slip prevention ( c sp), an ability to virtually eliminate cycle slipping during acquisition. when enabled, the c sp feature essentially holds the pfd gain at maximum until such time as the frequency difference is near zero. c sp allows signifcantly faster lock times as shown in figure 13. t he use of the c sp feature is enabled with pfds_rstb ( reg01<15> t able 12 ). t he c sp feature may be optimized for a given set of pll dynamics by adjusting the pfd sensitivity to cycle slipping. t his is achieved by adjusting pfds_sat_deltan ( reg1c<3:0> t able 38 ). c sp will cause the v co n divider to momentarily divide by a higher or lower n value in order to pull the divided v co phase back towards the reference edge. t he maximum recommended v co n divider deviation is no more than 20% of the target n value. for example, if n =50 for the target frequency, then the c sp magnitude should be 10 or less so r egister 1 c h bits [3:0] would be programmed to a h. i n situations where the target n value is low, for example 36 the c sp behavior will be compromised because the minimum v co divide value is 32 figure 13 . cycle slip prevention (csp)
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 18 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll c harge pump gain a simplifed diagram of the charge pump is shown in figure 14. c harge pump up and down gains are set by cp_ upcurrent_sel and cp_dncurrent_sel respectively ( reg07 t able 18 ). n ormally the registers are set to the same value. each of the up and d n charge pumps consist of 5-bit charge pumps with lsb of 125 a . t he current gain of the pump, in a mps/radian, is equal to the gain setting of this register divided by 2. for example if both cp_upcurrent_sel and cp_dncurrent_sel are set to 01000 the output current of each pump will be 1m a and the gain kp = 1m a /2 radians, or 159 u a /rad. c harge pump gain t rim i n most applications gain t rim is not used. however it is available for special applications. each of the up and d n pumps may be trimmed separately to more precise values to improve current source matching of the up and d n values, or to allow fner control of pump gain. t he pump trim controls are 3-bits, binary weighted for up and d n , in cp_uptrim_sel and cp_dntrim_sel respectively ( r eg 08h t able 19 ). lsb weight is 14.7 u a , x000 = 0 trim, x001 = 14.7 ua added trim, x111 = 100u a . c harge pump phase o ffset either of the up or d n charge pumps may have a d c leakage or offset added. t he leakage forces the phase detector to operate with a phase offset between the reference and the divided v co inputs. i t is recommended to operate with a phase offset when using fractional mode to reduce non-linear effects from the up and d n pump mismatch. phase noise in fractional mode is strongly affected by charge pump offset. d c leakage or offset may be added to the up or d n pumps using cp_upoffset_sel and cp_dnoffset_sel ( reg08 t able 19 ). t hese are 4 bit registers with 28.7u a lsb. maximum offset is 430u a . a s an example, if the main pump gain was set at 1m a , an offset of 373u a would represent a phase offset of about (392/1000)*360 = 133 degrees. for best spectral performance in fractional mode the leakage current should be programmed to: r equired leakage c urrent ( a ) = (2.5e-9 + 4x t vco) x fcomparison (hz) x c p current ( a ) figure 14 . charge pump gain, trim and phase offset control
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 19 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll frequency programming t he hm c 701lp6 c e can operate in either fractional mode or integer mode. i n integer mode of operation the delta sigma modulator is disabled. frequency programming and mode control is described below. fractional frequency t he fractional frequency synthesizer, when operating in fractional mode, can lock to frequencies which are fractional multiples of the reference frequency. fractional mode is the default mode. t o run in fractional mode ensure that dsm_integer_mode r eg12h<5> t able 29 is clear and dsm_rstb r eg01<13> t able 12 ). t hen program the frequency as explained below: t he output frequency of the synthesizer is given by, f vco , where fractional frequency of vco (eq 13) where n int is the integer division ratio, an integer number between 36 and 65,533 ( dsm_intg ( reg0fh t able 26 )) n frac is the fractional part, a number from 1 to 2 24 ( dsm_frac reg10h t able 27 ) r is the reference path division ratio, ( rfp_div_ratio reg03h<13:0> t able 14 ) f xtal is the frequency of the crystal oscillator input (xs in or x r ef figure 4) a s an example: f xtal = 50 mhz r = 1 f ref = 50 mhz n int = 46 n frac = 1 (eq 14) i n this example the output frequency of 2,300,000,002.98 hz is achieved by programming the 16-bit binary value of 46d = 2eh = 0000 0000 0010 1110 into dsm_intg . similarly the 24-bit binary value of the fractional word is written into dsm_frac , 1d = 000 001h = 0000 0000 0000 0000 0000 0001
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 20 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll example 2 : set the output to 4.600 025 ghz using a 100 mhz reference, r =2. find the nearest integer value, n int , n int = 92, f int = 4.600 000 ghz t his leaves the fractional part to be f frac =25 khz (eq 15) since n frac must be an integer number, the actual fractional frequency will be 25,001.17 hz, an error of 1.17 hz. here we program the 16-bit n int = 92d = 5 c h = 0000 0000 0101 1100 and the 24-bit n frac = 8389d = 20 c 5h = 0000 0010 0000 1100 0101 i n addition to the above frequency programming words, the fractional mode must be enabled using the frac register. o ther dsm confguration registers should be set to the recommended values. r egister setup fles are available on request. i nteger frequency t he synthesizer is capable of operating in integer mode. i n integer mode the digital ? modulator is normally shut off and the division ratio of the v co divider is set at a fxed value. t o run in integer mode set dsm_integer_mode ( reg12h<3> t able 29 ) and clear dsm_rstb ( reg01h<13> t able 12 ). t hen program the integer portion of the frequency, n int , as explained by (eq 13), ignoring the fractional part. frequency hopping t rigger i f the synthesizer is in fractional mode, a write to the fractional frequency register, reg10h t able 27 , will initiate the frequency hop on the falling edge of the 31 st clock edge of the serial port write (see figure 18). i f the integer frequency register, reg0fh t able 26 , is written when in fractional mode the information will be buffered and only executed when the fractional frequency register is written. i f the synthesizer is in integer mode, a write to the integer frequency register, reg0fh t able 26 , will initiate the frequency hop on the falling edge of the 31 st clock edge of the serial port write (see figure 18). power o n r eset (p or ) n ormally all logic cells in the hm c 701lp6 c e are reset when the device digital power supply, dvdd, is applied. t his is referred to as power o n r eset, or just p or . p or normally takes about 500us after the dvdd supply exceeds 1.5v, guaranteed to be reset in 1msec. o nce the dvdd supply exceeds 1.5v, the p or will not reset the digital again unless the supply drops below 100mv. soft r eset t he sp i registers may also be soft reset by an sp i write to strobe global_swrst_regs ( reg00h<0> t able 11 ). a ll other digital, including the fractional modulator, may be reset with an sp i write to strobe global_swrst_dig (reg00h<1> t able 11 ). hardware r eset t he sp i registers may also be hardware reset by holding r s t b, pin 19, low.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 21 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll power down t he hm c 701lp6 c e may be powered down by writing a zero to reg01h t able 12 . i n power down state the hm c 701lp6 c e should draw less than 10u a . i t should be noted that reg01h is the enable and r eset r egister which controls 16 separate functions in the chip. depending upon the desired mode of operation of the chip, not all of the functions may be enabled when in operation. hence power up of the chip requires a selective write to reg01 bits. a n easy way to return the chip to its prior state after a power down is to frst read reg01h and save the state, then write a zero to reg01h for reset and then simply rewrite the previous value to restore the chip to the desired operating mode. c w sweeper mode t he hm c 701lp6 c e features a built in frequency sweeper function. t his function supports external or automatic triggered sweeps. t he maximum sweep range is limited to 255 x fxtal/ r . for example, with a 25 mhz comparison frequency, the maximum sweep range is 6375 mhz. t he start and end frequency points must be within 6375 mhz of one another. for sweep operation the delta-sigma modulator mode should be feed forward ( r egister 12h bits [9:8] = 11) otherwise discontinuities may occur when crossing integer- n boundaries (harmonic multiples of the comparison frequency). sweeper modes include: a. 2-way sweep mode: alternating positive and negative frequency ramps. b. 1-way sweep mode c. single step r amp mode a pplications include test instrumentation, fm c w sensors, automotive radars and others. t he parameters of the sweep function are illustrated in figure 15. t he sweep generator is enabled with ramp_enable in ( reg14h<1> t able 30) . t he sweep function cycles through a series of discrete frequency values, which may be a. stepped by an automatic sequencer, or b. single stepped by individual triggers in single step mode. t riggering of each sweep, or step, may be confgured to operate: a. via a serial port write to reg14h<2> ramp_trigg (if r eg 14h<2> = 0 ) b. a utomatically generated internally, c. t riggered via tt l input on gp o 3 r eg14h<5> = 1. sweep parameters are set as follows: i nitial frequency, f o = c urrent frequency value of the synthesizer, ( eq 15 ) final frequency, f f = frequency of the synthesizer at the end of the ramp t he frequency step size while ramping is controlled by rampstep , ( reg15h t able 31 ). frequency step size ? step = rampstep ? f xtal / 2 24 ? r where r is the value of the reference divider ( rfp_div_ratio in t able 14 ) c learing or setting ramp_startdir_dn , ( reg14h<4> t able 30 ), sets the initial ramp direction to be increasing or decreasing in frequency respectively. setting ramp_singledir ( reg14h<7> t able 30 ), restricts the direction of the sweep to the initial sweep direction only. t he sweeper timebase t ref is the period of the divided reference, f pfd , at the phase detector t ref t he total number of ramp steps taken in a single sweep is given by ramp_steps_number in r eg16h t able 32 . t he total time to ramp from f o to f f is given by t ramp = t ref ? ramp_steps_number
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 22 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll c w sweeper mode (continued) t he fnal ramp frequency, f f , is given by ? ? = ? i + ? step ? ramp_steps_number sweeper action at the end of sweep depends upon the mode of the sweep: a. with both ramp_singledir and ramp_repeat_en disabled, at the end of the ramp time, t ramp , the sweeper will dwell at the fnal frequency f f , until a new trigger is received. t he next trigger will reverse the current sequence, starting from f f , and stepping back to f o . o dd triggers will ramp in the same direction as the initial ramp, even triggers will ramp in the opposite direction. b. with ramp_singledir enabled and ramp_repeat_en disabled, at the end of the ramp time, t ramp , the sweeper will dwell at the fnal frequency f f , until a new trigger is received. t he second trigger will hop the synthesizer back to the initial frequency, f o . t he third trigger will restart the sweep from f o . hence all odd numbered triggers will start a new ramp in the same direction as the initial ramp, even numbered triggers will hop the synthesizer from the current frequency to f o , where it will wait for a trigger to start a sweep. r amp busy i n all types of sweeps ramp_busy will indicate an active sweep and will stay high between the 1 st and n th ramp step. ramp_busy may be monitored one of two ways. ramp_busy is readable via read only register reg1fh<5> t able 41 . ramp_busy may also be monitored on gp o 2, hardware pin 24, by setting reg1bh<3:0> =8h t able 37 . a utosweep mode t he a utosweep mode is similar to figure 15 except that once started, triggers are not required. o nce enabled, ( ramp_ repeat_en=1 reg14h<3> t able 30 ) the a utosweep mode initiates the frst trigger, steps n times, one step per ref clock cycle, and then waits for the programmed dwell period and automatically triggers the ramp in the opposite direction. t he sweep process continues alternating sweep directions until disabled. dwell_time ( reg17h t able 33 ) controls the number of t ref periods to wait at the end of the ramp before automatically retriggering a new sweep. 2-way sweeps i f ramp_repeat_en ( reg14h<3> t able 30 ) is cleared, then the ramps are triggered by a. writing to ramp_trigg ( reg14h<2> t able 30 ), if bit <2> = 0, or b. by rising edge tt l signal input on gp o 3, if ramp_trig_ext_en is set, and gp o 3 is enabled. a ll functions are the same in figure 15 for a utosweep or 2-way t riggered sweeps, the only difference is the trigger source is generated internally for autosweep, and is input via serial port or gp o 3 for triggered sweeps. sweep_busy will go high at the start of every ramp and stay high until the nth step in the ramp.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 23 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll figure 15 . 2-way sweep control via trigger t riggered 1-way sweeps 1-way sweeps are shown infigure 16. unlike 2-way sweeps, 1-way sweeps require that the v co hop back to the start frequency after the dwell period. t riggered 1-way sweeps also require a 3 rd trigger to start the new sweep. t he 3 rd trigger must be timed appropriately to allow the v co to settle after the large frequency hop back to the start frequency. subsequent odd numbered triggers will start the 1-way sweep and repeat the process. figure 16 . 1-way sweep control
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 24 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll single step r amp mode a single step 1-way r amp is shown in figure 17. i n this mode, a trigger is required for each step of the ramp. single step will function in either 1-way or 2-way ramps. similar to autosweep, the ramp_busy fag will go high on the frst trigger, and will stay high until the nth trigger. t he n+1 trigger will cause the ramp to jump to the start frequency in 1-way ramp mode. t he n+2 trigger will restart the 1-way ramp. figure 17 . single step ramp mode t he user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. i f the loop bandwidth in use is much wider than the rate of the steps then the locking will be very fast and the ramp will have a staircase shape. i f the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not fully settle before a new frequency step is received. hence the swept output will have a small lag and will sweep in a near continuous fashion.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 25 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll m ain se rial p ort t he hm c 701lp6 c e features a four wire serial port for simple communication with the host controller. r egister types may be r ead o nly, write o nly, r ead/write or strobe, as described in the registers descriptions. t he synthesizer also features an auxiliary 3-wire serial port, known as the v co serial port. t he v co serial port is a write only interface from the synthesizer to an optional switched resonator v co that supports 3-wire serial port control. t ypical main serial port operation can be run with s c lk at speeds up to 50 mhz. serial port registers are described in the section r eg i s t e r m a p. serial port w rit e o peration a vdd = dvdd = 3v 10%, a g n d = dg n d = 0v t able 4. t iming c haracteristics parameter conditions min. typ. max units t 1 se n to s c lk setup time 8 nsec t 2 sd i to s c lk setup time 10 nsec t 3 sd i to c lk hold time 10 nsec t 4 s c lk high duration 8 nsec t 5 s c lk low duration 8 nsec t 6 se n high duration 640 nsec t 7 se n low duration 20 nsec a typical w rit e cycle is shown in figure 18. a. t he master (host) both asserts se n (serial port enable) and clears sd i to indicate a w rit e cycle, followed by a rising edge of s c lk. b. t he slave (synthesizer) reads sd i on the 1st rising edge of s c lk after se n . sd i low initiates the w rit e cycle (/w r ) c. host places the six address bits on the next six falling edges of s c lk, msb frst. d. slave registers the address bits in the next six rising edges of s c lk (2-7). e. host places the 24 data bits on the next 24 falling edges of s c k, msb frst . f. slave registers the data bits on the next 24 rising edges of s c k (8-31). g. se n is de-asserted on the 32nd falling edge of s c lk. h. t he 32 nd rising edge of s c lk completes the cycle figure 18 . serial port timing diagram - write
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 26 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll main serial port r e a d o peration t he synthesizer uses the multi-purpose pin, ld_sdo , for both lock detect and serial data o ut (sd o ) functions. t he registers lkd_to_sdo_automux_en (reg1a<12>) and lkd_to_sdo_always ( reg1a<13> t able 36 ) determine how the data o utput pin is muxed with the lock detect function. i f both of the registers are cleared, then the pin is exclusively sd o . i f automux is enabled, the pin switches to sd o when the r d function is sensed on the 1st rising edge of s c lk. i f lkd_to_sdo_always is set, then the pin ld_sdo is dedicated for lock detect only, and it is not possible to read from the synthesizer. a typical r e a d cycle is shown in figure 19. a. t he master (host) asserts both se n (serial port enable) and sd i to indicate a r e a d cycle, followed by a rising edge s c lk b. t he slave (synthesizer) reads sd i on the 1st rising edge of s c lk after se n . sd i high initiates the r e a d cycle ( r d) c. host places the six address bits on the next six falling edges of s c lk, msb frst. d. slave registers the address bits on the next six rising edges of s c lk (2-7). e. slave places the 24 data bits on the next 24 rising edges of s c k (8-31), msb frst . f. host registers the data bits on the next 24 falling edges of s c k (8-31). g. se n is de-asserted on the 32nd falling edge of s c lk. h. t he 32nd falling edge of s c lk completes the cycle figure 19 . serial port timing diagram - read
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 27 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll r eg i s t er m a p r eg 00h c hip i d ( r ead o nly) r egister bit type name width default description [23:0] r o c hip i d 24 581502 c hip i d t able 11. r eg 00h strobe (write o nly) r egister bit type name width default description 0 s tr global_swrst_regs 1 0 strobe to soft reset the sp i registers 1 s tr global_swrst_dig 1 0 strobe to soft reset the rest of digital 2 s tr mcnt_resynch 1 0 r eserved 3 s tr tsens_spi_strobe 1 0 strobe to clock the temp measurement on demand t able 12. r eg 01h enable & r eset r egister bit type name default description 0 r /w malg_vcobug_en 1 1 v co buffer enable 1 r /w mag_bias_en 1 1 bias enable 2 r /w rfp_div_en 1 0 enables / holds refdiv in reset holding r ef divider in reset is equivalent to bypassing the divider, see figure 4 3 r /w xrefmux_todig_en 1 1 enables clock gate for xtal muxed (sq or sin) reference to digital 4 r /w rfp_div_todig_en 1 0 enables divided reference clock to the digital see figure 4 5 r /w rfp_sqr_todig_en 1 0 enables square wave xtal clock to main digital see figure 4 6 r /w rfp_sin_todig_en 1 0 enables sine wave xtal clock to main digital see figure 4 7 r /w rfp_bug_sq_en 1 1 enables square wave r ef buffer, see figure 4 8 r /w rfp_bug_sin_en 1 0 enables sine wave r ef buffer, see figure 4 9 r /w vcop_todig_en 1 0 1= divided v co as digital, ? modulator clock 0= divided r ef path as the 10 r /w vcop_presc_en 1 1 enables the prescaler bias 11 r /w pfd_lkd_en 1 0 enable / r esetb to digital lockdetect circuit and pfds lockdetect output gates 12 r /w cp_en 1 1 c harge pump enable, disable is tri-stated output 13 r /w dsm_rstb 1 0 1 - enables fractional modulator see also dsm_integer_mode reg12h<3> 14 r /w lkd_rstb 1 0 1 - enables lock detect circuit 15 r /w pfds_rstb 1 1 c sp pfd ff rstb 1 - enables the c ycle slip prevention ( c sp) feature of the pfd
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 28 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 13. r eg 02h serial data o ut force r egister bit type name default description 0 r /w malg_sdo_driver_force_val 1 serial data o ut force value t his value may be forced onto ld_sd o by setting malg_sdo_driver_force_en 1 r /w malg_sdo_driver_force_en 1 serial data o ut e n force enable places value from malg_sdo_driver_force_val on sd o t able 14. r eg 03h r eference path r egister bit type name default description 13:0 r /w rfp_div_ratio also referred to as r 0 divides the crystal input by this number r if rfp_div_en=1 and rfp_div_select = 1 rfp_div_ratio = 0 not allowed 2<=div_ratio<=2^14 see figure 4 14 r /w rfp_div_select 0 1 = reference divider enabled 0 = bypass ref divider see figure 4 15 r /w rfp_auto_refdiv_sel_en 0 1 = auto ref divider enable or bypass is automatic if rfp_div_ratio = 1, bypass divider if rfp_div_bypass ~=1 use divider see figure 4 16 r /w rfp_buf_sin_sel 0 selects sine wave reference for normal operation see figure 4 t able 15. r eg 04h prescaler duty c ycle r egister bit type name default description 0 r /w vcop_dutycycmode 0 extends the low time from 15 to 47 v co cycles for large divide ratios t able 16. r eg 05h phase freq detector r egister (pfd) bit type name default description 0 r /w pfd_phase_sel 0 i nverts pfd polarity 0 = passive filter +ve slope v co 1 = passive filter -ve slope v co 1 = a ctive inverting flter, +ve slope v co 0 = a ctive inverting flter, -ve slope v co 1 r /w pfd_upout_en 1 a llows masking of the up outputs between pfd and c p 2 r /w pfd_dnout_en 1 a llows masking of the dn outputs between pfd and c p t able 17. r eg 06h phase freq detector delay r egister bit type name default description 2:0 r /w pfd_del_sel 2 delay line setpoint to pfd
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 29 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 18. r eg 07h c harge pump up/d n c ontrol r egister bit type name default description 4:0 r /w cp_upcurrent_sel 16 sets c harge-pump up gain, 125u a lsb, binary, 4m a max 9:5 r /w cp_d n current_sel 16 sets c harge-pump dn gain, 125u a lsb, binary, 4m a max t able 19. r eg 08h c harge pump t rim & o ffset r egister bit type name default description 3:0 r /w cp_uptrim_sel 0 t rim up gain, 14.3u a lsb, binary, 100u a max 7:4 r /w cp_d n trim_sel 0 t rim dn gain, 14.3u a lsb, binary, 100u a max 11:8 r /w cp_upoffset_sel 4 up o ffset leakage current, 28.7u a lsb, binary, 430u a max 15:12 r /w cp_d n offset_sel 0 dn o ffset leakage current, 28.7u a , binary, 430u a max 17:16 r /w cp_amp_bias_sel 2 c harge pump dummy branch o p amp bias selection, 100u a t able 20. r eg 09h c harge pump e n r egister bit type name default description 0 r /w cp_pull_updn_en 0 enables c p up/down c ontrol r eg09 [1] 1 r /w cp_pull_dn_upb 0 0 - forces c harge pump up when r eg09[0]=1 1 - forces c harge pump d n when r eg09[0]=1 t able 21. r eg 0 a h r eserved bit type name default description 23:0 r /w r eserved 0 r eserved t able 22. r eg 0bh r eserved bit type name default description 23:0 r /w r eserved 0 r eserved t able 23. r eg 0 c h r eserved bit type name default description 23:0 r /w r eserved 0 r eserved t able 24. r eg 0dh r eserved bit type name default description 23:0 r /w r eserved 0 r eserved t able 25. r eg 0eh r eserved bit type name default description 23:0 r /w r eserved 0 r eserved
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 30 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 26. r eg 0fh i nteger division r egister bit type name default description 15:0 r /w dsm_intg 200d unsigned integer portion of v co divider value, also known as n int , see ( eq 12 ) t able 27. r eg 10h fractional division r egister bit type name default description 23:0 r /w dsm_frac 0 unsigned fractional portion of v co divider also known as n frac , see ( eq 12 ) t able 28. r eg 11h seed r egister bit type name default description 23:0 r /w dsm_seed 0 unsigned seed value for ? modulator sets the start phase of the modulator t able 29. r eg 12h delta sigma modulator r egister bit type name default description 0 r /w dsm_ref_clk_select 0 use reference instead of divider 1 r /w dsm_invert_clk_sd3 1 invert ? clk 2 r /w dsm_invert_clk_rph 0 inverts the ref clock phase 3 r /w dsm_integer_mode 0 1- enables i nteger mode, bypasses the ? modulator, leaves it running see also dsm_rstb r eg01h<13> to disable the modulator 4 r /w r eserved 0 5 r /w r eserved 0 6 r /w dsm_xref_sin_select 0 when xref is selected specifes that the sine source is used 7 r /w dsm_autoseed 1 automatic seed load when changing the frac part, uses value in seed 9:8 r /w dsm_order 2 00-frst order 01-second 10-third fb 11-third ff 13:10 r /w dsm_quant_max 4b0111 max value allowed out of ? modulator quantizer limits are +7 to -8, typ 3 or 4 17:14 r /w dsm_quant_min 4b1000 min value allowed out of ? modulator quantizer limits are +7 to -8, typ 3 or 4
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 31 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 30. r eg 14h c w sweep c ontrol r egister t he maximum sweep range is limited to 255 x fxtal/ r . delta-sigma modulator mode should be feed forward when using sweep feature ( r egister 12h bits [9:8] = 11. bit type name default description 0 r /w clear_ovf_undf 0 asynchronous clear for ovf/undf fags 1 r /w ramp_enable 0 r amp en/rstb 1= enables the c w r amp function 2 r /w ramp_trigg 0 write always triggers ramps if bit <2> = 0, if bit <2> = 1, r amp will not trigger, bit <2> must be reset to 0 frst 3 r /w ramp_repeat_en 0 r amp r epeat seq enable 1= enables autotrigger of ramps 0 = ramp_trigg starts each ramp 4 r /w ramp_startdir_dn 0 r amp start direction 1= start with r amp down 0= start with r amp up 5 r /w ramp_trig_ext_en 0 enable hardware trigger on gp o 3 pin 6 r /w ramp_singlestep 0 r amp single step, advances the ramp to the next step, and holds frequency 7 r /w ramp_singledir 0 r amps in one direction only with hop to start at end of ramp t able 31. r eg 15h c w sweep r amp step r egister t he maximum sweep range is limited to 255 x fxtal/ r . delta-sigma modulator mode should be feed forward when using sweep feature ( r egister 12h bits [9:8] = 11. bit type name default description 23:0 r /w ramp_step 2048 r amp step size t able 32. r eg 16h c w sweep r amp step n umber r egister t he maximum sweep range is limited to 255 x fxtal/ r . delta-sigma modulator mode should be feed forward when using sweep feature ( r egister 12h bits [9:8] = 11. bit type name default description 23:0 r /w ramp_steps_number 2048 r amp n umber of steps in ramp t able 33. r eg 17h c w sweep dwell t ime r egister bit type name default description 23:0 r /w ramp_dwell_time 2048 r amp n umber of cycles to hold at top/bottom in repeat mode [1] phase-error measurement and c ompensation in pll frequency synthesizers for fm c w, sensors i : c ontext and a pplication, pichler, stelzer, member, i eee, seisenberger, and vossiek, i eee t ransactions on c ircuits and systems i , v o l. 54, n o. 5, may 2007
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 32 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 34. r eg 18h a uxiliary o scillator r egister 1 bit type name default description 1:0 r /w dsmclk_auxclk_insel 0 selects the input clk for auxclk 0:vcodiv 1:xrefsq or sin 2:refdiv 3:ring oscillator from mono, est 300 mhz to 1 ghz 3:2 r /w dsmclk_auxclk_modesel 0 0: bypass-no delay 1: pass through w/ delay 2: ring-out constant 3: ring-out seeded/gated 6:4 r /w dsmclk_auxclk_divsel 2 divider selection auxclk value divby 000 001 010 011 100 101 110 111 1 2 4 6 8 10 12 14 7 r /w dsmclk_auxclk_sel 0 selects auxclk (if=1) as natural reference clk input of sigma delta 8 r /w dsmclk_auxmod_lfsr_en 0 enables 10-bit lfsr inside the delay modulator (clocked by auxclk or auxclkb) 9 r /w dsmclk_auxmod_accum_en 0 enables 8-bit accumulator inside the delay modulator (clocked by auxclk or auxclkb) 11:10 r /w dsmclk_auxmod_mode 0 delay modulation mode 0: auxmod_lodly_in passthrough 1: accumulator based square-wave 2: lfsr (lo-amp) 3: lfsr (hi-amp) 19:12 r /w dsmclk_auxmod_fracstep 3 step-size of accumulator (changes square-wave value once it wraps through 256) 22:20 r /w dsmclk_auxmod_lodly 0 value of delay-element (when auxmod_mode=0) or low value used during sq-wave modulation t able 35. r eg 19h a uxiliary o scillator r egister 2 bit type name default description 2:0 r /w dsmclk_auxmod_hidly 7 hi value of delay element during sq-wave modulation 3 r /w dsmclk_auxmod_clkinv 1 optionally inverts auxclk as used by the modulator 4 r /w dsmclk_auxmod_clkwring 9 select lkd ringosc to clock the lfs r
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 33 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 36. r eg 1 a h l ock detect r egister bit type name default description 9:0 r /w lkd_wincnt_max 10d40 threshold count in the timer window to declare lock (reference cycles) 10 r /w lkd_win_asym_enable 0 enables asymmetric lock detect window (nominal 10nsec) 11 r /w lkd_win_asym_up_select 0 sets polarity of the window 12 r /w lkd_to_sdo_automux_en 0 muxes the lkd output signal to sd o when sd o is not being used for main serial port data o utputs ( r ead o peration) 13 r /w lkd_to_sdo_always 0 muxes the lkd output signal to sd o always, not possible to do main serial port r ead in this state 14 r /w lkd_ringosc_mono_select 0 1 select ringosc based oneshot for lock detect window 0 selects analog based oneshot 16:15 r /w lkd_ringosc_cfg 0 00 fastest 11 slowest 18:17 r /w lkd_monost_duration 0 00 shortest 11 longest 19 r /w lkd_ringosc_testmode 0 enables the ring osc by itself for testing
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 34 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 37. r eg 1bh gp o c ontrol r egister bit type name default description 3:0 r /w gpo_sel 0 selects data to be driven on gp o ports gpo_sel<3:0> = 0000 gp o 3 <=gposel_0_data<2> gp o 2 <= gposel_0_data<1> gp o 1 <= gposel_0_data<0> gpo_sel<3:0> = 0001 gp o 3 <= xref_clk_in gp o 2 <= ref_clk_in gp o 1 <= vco_div_clkin gpo_sel<3:0> = 0010 gp03 <= pfd_up_in gp02 <= pfd_dn_in gp01 <= lkd_monost_window gpo_sel<3:0> = 0011 gp03 <= pfd_sat_ref_in gp02 <= pfd_sat_vco_div_in gp01 <= delta_integer_cycslip_sel, this strobe holds the gain of the pfd at max for anti-cycle slipping gpo_sel<3:0> = 0100 gp03 <= xref_clk_in gp02 <= xref_sin_in gp01 <= sd_frac_strobe_sync, internally synchronized frac strobe gpo_sel<3:0> = 0101 r eserved gpo_sel<3:0> = 0110 gp03 <= sd_ i ntz1<1> gp02 <=sd_ i ntz1<2> gp01 <= sd_ i ntz1<3> 3-bit quantized version of the v co phase gpo_sel<3:0> = 0111 gp03 <= aux_clk gp02 <= ringosc_test gp01 <= clk_sd gpo_sel<3:0> = 1000 gp03 <= 00 gp02 <= ramp_busy gp01 <= r eserved gpo_sel<3:0> = 1001 r eserved gpo_sel<3:0> = 1010 gp03 <= ? quantizer o utput 3rd lsb gp02 <= ? quantizer o utput 2nd lsb gp01 <= ? quantizer o utput lsb 6:4 r /w gpo_sel_0_data this data is driven on gpo if gpo_sel==0 7 r /w gpo_dig_drive_en enables t ri-state drivers on gp o output pads 10:8 r /w gpo_ind_drive_dis 000 = all gp o pad drivers enabled xx1 = disable gp o 1 pad driver x1x = disable gp o 2 pad driver 1xx = disable gp o 3 pad driver
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 35 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 38. r eg 1 c h phase detector c sp r egister bit type name default description 3:0 r /w pfds_sat_delta n 5d4 0= c ycle slip prevention ( c sp) disabled 4-bit value to advance or retard phase detector in v co cycles if it reaches 2pi , i.e. cycle slip prevention. 1st bit is polarity, enabled by rstb 4 r /w pfds_rstb_force 0 c sp pfd flip-fops r s t b: 1 - controlled by the pfds_rstb bit: 0 - auto-controlled by the c sp logic forces the pfd into reset, which tristates charge pump, freezes charge on the loop flter, and hence opens the loop 5 r /w pfds_rstb 1 c sp pfd ff rstb 1 - enables the c ycle slip prevention ( c sp) feature of the pfd t able 39. r eg 1dh r eserved bit type name default description 23:0 r /w r eserved 0 r eserved t able 40. r eg 1eh t emperature sensor r egister bit type name default description 0 r /w tsens_spi_enable 0 enable the temperature sensor, draws ~2m a current, must strobe tsens_spi_strobe r eg 00h <3> t able 41. r eg 1fh l d, v co & r amp busy r ead o nly r egister bit type name default description 0 ro ro_lock_detect 0 1 = locked, 0 = unlocked 3:1 ro ro_dsm_overfow 0 1 = modulator overfow 4 ro r eserved 0 r eserved 5 ro ro_ramp_busy 0 sweeper status fag, set when ramp is busy, cleared when at end of ramp or not used t able 42. r eg 20h r eserved bit type name default description 23:0 ro r eserved 0 r eserved t able 43. r eg 21h t emperature sensor r ead o nly r egister bit type name default description 6:0 ro tsens_temperature 0 c urrent t emperature from temp sensor lsb = 17.5 c 0000111 = t emp >= 82.5 c 0000110 = t emp 0000000 = t emp <=-22.5 c tsens_temperature = foor (( t emp+40)/17.5)
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - sm t 0 0 - 36 hmc701lp6ce v07.0411 8 ghz 16-bit fractional- n p ll t able 44. r eg 22h a utotune r esult r egister bit type name default description 23:0 ro r eserved 0 r eserved o utline drawing not es: 1. p ac k a ge b o dy m at e ria l: l o w s tr ess in je ction m o lded pl a s tic s i l ica an d s i l icon i mp r eg nat ed. 2. le a d an d g ro u n d p a ddle m at e ria l: co ppe r a ll o y. 3. le a d an d g ro u n d p a ddle pl atin g: 100% m att e tin . 4. d i me n s ion s ar e in inc hes [m i ll i me t e r s]. 5. le a d sp acin g to le ranc e i s non - c umul ati ve. 6. p a d bu rr le n g t h sh a ll be 0.15mm m a x. p a d bu rr he i gh t sh a ll be 0.25mm m a x. 7. p ac k a ge w ar p sh a ll not ex c eed 0.05mm 8. a ll g ro u n d le a ds an d g ro u n d p a ddle mus t be s o lde r ed to p c b r f g ro u n d. 9. r efe r to h ittit e a ppl ication not e f or sugges t ed p c b l an d p att e rn . part n umber package body material lead finish msl r ating package marking [1] hm c 701lp6 c e r ohs-compliant low stress i njection molded plastic 100% matte sn msl1 [2] h701 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c package i nformation

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